library IEEE; use IEEE.std_logic_1164.all;
entity toplevel is
	port (
		sw: in std_logic_vector(3 downto 0);
        led: out std_logic_vector(3 downto 0) );
end entity toplevel;

architecture kodutoo1 of toplevel is
	component f_system
    port ( x1, x2, x3, x4: in std_logic;
           y1, y2, y3, y4: out std_logic );
  	end component;
	for U1: f_system use entity work.f_system(tabel);
begin
	U1: f_system port map (sw(3), sw(2), sw(1), sw(0), led(3), led(2), led(1), led(0));
end kodutoo1;