Basics of digital systems modeling and verification.
Equivalence-checking, model-checking, simulation. Verification methods,
simulation versus formal verification, code coverage, synthesizability.
Modeling and verification languages - SystemC, SystemVerilog, VHDL,
PSL. Coding for verification, problems with those languages.
- Õpetaja/Teacher: Peeter Ellervee
- Õpetaja/Teacher: René Pihlak
- Õpetaja/Teacher: Jaan Raik