IAS0600 Digital Systems Design with VHDL (2022)

Course: IAS0600 Digital Systems Design with VHDL (2022) | Moodle

• General

  
  

  • Hello everyone!

    Welcome to the Digital Systems Design with VHDL course. Nowadays digital systems are everywhere. There are more electronic components in modern cars than mechanical parts. You might already know how to design digital systems using schematic diagrams, but in this course, we will learn how to create them using hardware description language such as VHDL. Digital circuits created during the practical classes will be implemented on FPGAs. FPGAs (Field Programmable Gate Arrays) are an example of reconfigurable computing systems that are gaining more and more popularity these days.
    

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    Course info (link to study information system) URL
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    Extended syllabus File
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    Course schedule Page

    The detailed schedule of the course with topics covered during the lectures and corresponding labs.

  • Grading system

    Total points = Lab points + Exam + Bonus points = 60 + 40 + 10
    

  • Recommended reading

    • Volnei A. Pedroni, Circuit Design and Simulation with VHDL, The MIT Press, 2010.
    • Sarah L. Harris & David M. Harris, Digital Design and Computer Architecture, Elsevier, 2016.
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    Course participant's forum (ask questions from a teacher/other participants)
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    News forum
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    Feedback
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  Instructions: Clicking on the section name will show / hide the section.

  

• Usefull resources

  • Board files

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    Nexys 4 DDR FPGA Board Reference Manual File
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    Nexys 4 DDR FPGA Board Constraints File
  • Guides

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    Xilinx Vivado IDE User Guide File
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    Coding guide File
  • Materials from previous years

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    Lecture slides from previous years URL
  Topic
  1
• Week 1. Course overview

  • This week we will talk about the course organization, grading system, and lab schedule. There will be no practice.

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    Course overview File
  Topic
  2
• Week 2. Introduction to VHDL. Lab tutorial 1

  • During the lecture, we will talk about the hardware description languages and the basics of the VHDL.

    During the practice, we will do the first lab tutorial. It will introduce Vivado IDE which we will use throughout the course. We will learn how to create a design entity and verify it using a testbench.

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    Introduction to VHDL File
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    Lab tutorial 1 File
  Topic
  3
• Week 3. Introduction to FPGA. Lab tutorial 2

  • During the lecture, we will talk about reconfigurable computing and FPGA as an example of reconfigurable hardware. The link below points to the Xilinx webpage dedicated to numerous FPGA applications.

    During the practice, we will do the second lab tutorial. It will show how to automate the output verification during the simulation and how to synthesize the created design and implement it on the FPGA board. Save files from the folder below to the lab computer, we will need them for the tutorial.

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    Source files for lab tutorial 2 Folder
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    Introduction to FPGA File
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    Lab tutorial 2 File
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    FPGA Applications (Xilinx) URL
  Topic
  4
• Weeks 4 & 5. Dataflow modeling style. Lab 1

  • During the lecture, we will talk about dataflow modeling style and concurrent statements. For the lab, you will design a 2-bit comparator.

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    Dataflow modeling style File
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    Lab 1. Comparator File
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• Weeks 6 & 7. Structural design. Lab 2

  • During the lecture, we will talk about structural modeling style, use of the components, and block design in Vivado. For the lab, you will implement a 2-bit adder.

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    Structural design File
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    Lab 2. 2-bit Adder File
  • Lab notes:

    1. Make sure that the name of your block design is different from the name of your VHDL file for the 2-bit adder.

    2. If you do some changes in the block design after creating the HDL wrapper, right-click on the block design file and select Create HDL wrapper again. This will force Vivado to update created HDL files accordingly.

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• Weeks 8 & 9. Behavioral modeling style. Lab 3

  • During the lecture, we will talk about behavioral modeling style, processes, and sequential logic. For the lab, you will implement a counter that counts how many times the button was pressed.

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    Behavioral modeling style File
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    Lab 3. Counter File
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• Weeks 10 & 11. Review. Lab 4

  • There will be no lecture during these weeks. Lab 4 is designed to test the knowledge you gained during the first half of the course. For the lab, you will need to implement a creeping line with your student code on 8 seven-segment displays. Read the manual carefully and build your design following the suggested steps. They will help you to create a considerably complex design in a comprehensive manner.

    Additionally, you can test your knowledge using the self-assessment quiz below. The quiz is optional and it will not affect your grade.
    

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    Lab 4. Creeping line File
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    Review quiz
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• Weeks 12 & 13. Parametric design. Lab 5

  • During the lecture, we will talk about complex arithmetic circuits and different ways to make your design parameterizable. For the lab, you will implement a parameterizable multiplier.
    

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    Arithmetic circuits and parametric design File
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    Lab 5. Multiplier File
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• Weeks 14, 15 & 16. Finite State Machines. Lab 6

  • During the lecture, we will talk about Finite State Machines (FSM) to control the datapath to design complex sequential circuits. For the lab, you will implement a greatest common divisor algorithm.

    Take a look at the attached example of a simple calculator created using FSM and datapath. The archive contains VHDL files that you can simulate and an algorithmic graph. It will help you with the lab.
    

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    Finite State Machine and Datapath File
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    Lab 6. FSMD File
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    FSMD_Example File
  Topic
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