Kursus: IAS0600 Digital Systems Design with VHDL (2022), Section: Weeks 4 & 5. Dataflow modeling style. Lab 1 | Moodle

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    • Hello everyone!

      Welcome to the Digital Systems Design with VHDL course. Nowadays digital systems are everywhere. There are more electronic components in modern cars than mechanical parts. You might already know how to design digital systems using schematic diagrams, but in this course, we will learn how to create them using hardware description language such as VHDL. Digital circuits created during the practical classes will be implemented on FPGAs. FPGAs (Field Programmable Gate Arrays) are an example of reconfigurable computing systems that are gaining more and more popularity these days.


    • Course info (link to study information system) URL
    • Extended syllabus Fail
    • Course schedule Lehekülg

      The detailed schedule of the course with topics covered during the lectures and corresponding labs.

    • Grading system

      Total points = Lab points + Exam + Bonus points = 60 + 40 + 10

    • Recommended reading

      • Volnei A. Pedroni, Circuit Design and Simulation with VHDL, The MIT Press, 2010.
      • Sarah L. Harris & David M. Harris, Digital Design and Computer Architecture, Elsevier, 2016.
    • Course participant's forum (ask questions from a teacher/other participants) Foorum
    • News forum Foorum
Week 3. Introduction to FPGA. Lab tutorial 2
Weeks 6 & 7. Structural design. Lab 2

Weeks 4 & 5. Dataflow modeling style. Lab 1

  • Weeks 4 & 5. Dataflow modeling style. Lab 1

    • During the lecture, we will talk about dataflow modeling style and concurrent statements. For the lab, you will design a 2-bit comparator.

    • Dataflow modeling style Fail
    • Lab 1. Comparator Fail
Week 3. Introduction to FPGA. Lab tutorial 2
Weeks 6 & 7. Structural design. Lab 2