Section: Weeks 14, 15 & 16. Finite State Machines. Lab 6 | IAS0600 Digital Systems Design with VHDL (2022) | Moodle

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    • Hello everyone!

      Welcome to the Digital Systems Design with VHDL course. Nowadays digital systems are everywhere. There are more electronic components in modern cars than mechanical parts. You might already know how to design digital systems using schematic diagrams, but in this course, we will learn how to create them using hardware description language such as VHDL. Digital circuits created during the practical classes will be implemented on FPGAs. FPGAs (Field Programmable Gate Arrays) are an example of reconfigurable computing systems that are gaining more and more popularity these days.


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      The detailed schedule of the course with topics covered during the lectures and corresponding labs.

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      Total points = Lab points + Exam + Bonus points = 60 + 40 + 10

    • Recommended reading

      • Volnei A. Pedroni, Circuit Design and Simulation with VHDL, The MIT Press, 2010.
      • Sarah L. Harris & David M. Harris, Digital Design and Computer Architecture, Elsevier, 2016.
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Weeks 12 & 13. Parametric design. Lab 5

Weeks 14, 15 & 16. Finite State Machines. Lab 6

  • Weeks 14, 15 & 16. Finite State Machines. Lab 6

    • During the lecture, we will talk about Finite State Machines (FSM) to control the datapath to design complex sequential circuits. For the lab, you will implement a greatest common divisor algorithm.

      Take a look at the attached example of a simple calculator created using FSM and datapath. The archive contains VHDL files that you can simulate and an algorithmic graph. It will help you with the lab.

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      Finite State Machine and Datapath File
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      Lab 6. FSMD File
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      FSMD_Example File
Weeks 12 & 13. Parametric design. Lab 5