Kursus: IAS0600 Digital Systems Design with VHDL (2022), Jaotis: Weeks 6 & 7. Structural design. Lab 2 | Moodle

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    • Hello everyone!

      Welcome to the Digital Systems Design with VHDL course. Nowadays digital systems are everywhere. There are more electronic components in modern cars than mechanical parts. You might already know how to design digital systems using schematic diagrams, but in this course, we will learn how to create them using hardware description language such as VHDL. Digital circuits created during the practical classes will be implemented on FPGAs. FPGAs (Field Programmable Gate Arrays) are an example of reconfigurable computing systems that are gaining more and more popularity these days.


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      Course info (link to study information system) URL
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      Extended syllabus Fail
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      Course schedule Lehekülg

      The detailed schedule of the course with topics covered during the lectures and corresponding labs.

    • Grading system

      Total points = Lab points + Exam + Bonus points = 60 + 40 + 10

    • Recommended reading

      • Volnei A. Pedroni, Circuit Design and Simulation with VHDL, The MIT Press, 2010.
      • Sarah L. Harris & David M. Harris, Digital Design and Computer Architecture, Elsevier, 2016.
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      Course participant's forum (ask questions from a teacher/other participants) Foorum
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Weeks 4 & 5. Dataflow modeling style. Lab 1
Weeks 8 & 9. Behavioral modeling style. Lab 3

Weeks 6 & 7. Structural design. Lab 2

  • Weeks 6 & 7. Structural design. Lab 2

    • During the lecture, we will talk about structural modeling style, use of the components, and block design in Vivado. For the lab, you will implement a 2-bit adder.

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      Structural design Fail
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      Lab 2. 2-bit Adder Fail

    • Lab notes:

      1. Make sure that the name of your block design is different from the name of your VHDL file for the 2-bit adder.

      2. If you do some changes in the block design after creating the HDL wrapper, right-click on the block design file and select Create HDL wrapper again. This will force Vivado to update created HDL files accordingly.

Weeks 4 & 5. Dataflow modeling style. Lab 1
Weeks 8 & 9. Behavioral modeling style. Lab 3