Week Lecture Practice
#1 (31.08.22) Course overview
  • Topics
  • Hardware and software
  • Schedule
  • Labs overview
  • Report requirements
  • Grading system
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#2 (07.09.22) Introduction to VHDL
  • Hardware description languages vs software programming languages
  • VHDL history
  • Synthesizable vs non-synthesizable
  • Types, objects, operators
  • Design entity
 Lab tutorial 1
  • Vivado overview
  • How to create a new project
  • Design sources
  • Testbench and simulation
#3 (14.09.22) Introduction to FPGA
  • Reconfigurable hardware
  • FPGA architecture
  • FPGA design flow
 Lab tutorial 2
  • Assertions
  • Synthesis and implementation
#4 (21.09.22) Dataflow modeling style
  • Modeling styles in VHDL
  • Dataflow modeling
  • Concurrent signal assignments
  • Assertions
  • Functions
 Lab 1. 2-bit comparator
#5 (28.09.22) — Lab 1. 2-bit comparator
#6 (05.10.22) Structural design
  • Structural modeling style
  • Component instantiation
  • Type conversion
 Lab 2. 2-bit adder
#7 (12.10.22) — Lab 2. 2-bit adder
#8 (19.10.22) Behavioral modeling style
  • Processes
  • Signals vs variables
  • Sequential statements
  • Sequential logic
 Lab 3. Counter
#9 (26.10.22) — Lab 3. Counter
#10 (02.11.22) (No new topic is introduced in lab 4. It requires students to use the knowledge gained through the first three labs.) Lab 4. Creeping line
#11 (09.11.22) — Lab 4. Creeping line
#12 (16.11.22) Parametric design
  • Complex arithmetic circuits
  • Multiplier model
  • Parametric design
  • Generate statement
  • Complex types
 Lab 5. Parameterizable multiplier
#13 (23.11.22) — Lab 5. Parameterizable multiplier
#14 (30.11.22) Finite State Machines
  • FSM overview
  • FSM for hardware design
  • Datapath
  • FSM controller
  • Latch inference
 Lab 6. Greatest common divisor
#15 (07.12.22) — Lab 6. Greatest common divisor
#16 (14.12.22) — Lab 6. Greatest common divisor
Last modified: Monday, 19 December 2022, 5:30 PM