Xilinx Vivado

Vivado käivitamine

• Ava uus terminal
• Sisesta 2x käsk "cad"
• Vajuta numbrit valiku "Xilinx Vivado Desing Suite xxx" ees (2019 õppeaastal number "4")
• Käivitamiseks anna käsk "vivado"

Uue projekti seadmistamine

• File -> Project -> New -> Next
• Create a New Vivado Project: Next
• Project name: Anna projektile nimi, vali sobiv asukoht -> Next
• Project Type: RTL project (default) -> Next
• Add Sources: -> Next 
• Add Constraints (optional): -> Next
• Default part: Boards -> Vendor -> digilentinc.com -> Basys 3
• New Project Summary: Finish

Piirangute fail XDC

Võrreldes varasemate FPGA arenduplaatidega on UCF (user constraints file) ehk kasutaja piirangute fail asendatud XDC failiga. Tegu failiga, mis sisaldab arendusplaadi riistvara ressursside nimesid, aadresse jms. Fail on vajalik selleks, et siduda tarkvara komponendi sisendid ja väljundid plaadil olevate sisendite ja väljunditega. Digilent XDC failid (k.a. Basys 3).

Rohkem infot failide erinevusest on leitav siit. Peamised erinevused:

There are key differences between Xilinx Design Constraints (XDC) and User Constraints File
(UCF) constraints. XDC constraints are based on the standard Synopsys Design Constraints
(SDC) format. SDC has been in use and evolving for more than 20 years, making it the most
popular and proven format for describing design constraints. If you are familiar with UCF
but new to XDC, see the "Differences Between XDC and UCF Constraints" section in the
“Migrating UCF Constraints to XDC” chapter of the Vivado Design Suite Methodology Guide
(UG911). That chapter also describes how to convert existing UCF files to XDC as a starting
point for creating XDC constraints.